General Description

This device is an 8-bit serial shift register which shifts data

in the direction of QA toward QH when clocked. Parallel-in

access is made available by eight individual direct data

inputs, which are enabled by a low level at the shift/load

input. These registers also feature gated clock inputs and

complementary outputs from the eighth bit.

Clocking is accomplished through a 2-input NOR gate, permitting

one input to be used as a clock-inhibit function.

Holding either of the clock inputs HIGH inhibits clocking,

and holding either clock input LOW with the load input

HIGH enables the other clock input. The clock-inhibit input

should be changed to the high level only while the clock

input is HIGH. Parallel loading is inhibited as long as the

load input is HIGH. Data at the parallel inputs are loaded

directly into the register on a HIGH-to-LOW transition of the

shift/load input, regardless of the logic levels on the clock,

clock inhibit, or serial inputs.

特性 Features

n Complementary outputs

n Direct overriding (data) inputs

n Gated clock inputs

n Parallel-to-serial data conversion

n Typical frequency 35 MHz

n Typical power dissipation 105 mW