General Description

These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data.

特性 Features

■ Gated (enable/disable) serial inputs

■ Fully buffered clock and serial inputs

■ Asynchronous clear

■ Typical clock frequency 36 MHz

■ Typical power dissipation 80 mW