74AUP1G373GW屬于集成電路（IC）的鎖存器。由安世半導(dǎo)體(中國)有限公司制造生產(chǎn)的74AUP1G373GW鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

1. General description

The 74AUP1G373 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs

makes the circuit tolerant of slower input rise and fall times. This device ensures very low static

and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is

fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output,

preventing the potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

? Wide supply voltage range from 0.8 V to 3.6 V

? High noise immunity

? CMOS low power dissipation

? Low static power consumption; ICC = 0.9 μA (maximum)

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial Power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F Class 3A exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V

? CDM JESD22-C101E exceeds 1000 V

? Multiple package options

? Specified from -40 °C to +85 °C and -40 °C to +125 °C