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首頁>74AUP1G34-Q100>規(guī)格書詳情

74AUP1G34-Q100中文資料安世數(shù)據(jù)手冊(cè)PDF規(guī)格書

74AUP1G34-Q100
廠商型號(hào)

74AUP1G34-Q100

功能描述

Low-power buffer

文件大小

219.44 Kbytes

頁面數(shù)量

13

生產(chǎn)廠商

NEXPERIA Nexperia B.V. All rights reserved

中文名稱

安世 安世半導(dǎo)體(中國)有限公司

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-9-1 8:18:00

人工找貨

74AUP1G34-Q100價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

74AUP1G34-Q100規(guī)格書詳情

1. General description

The 74AUP1G34-Q100 is a single buffer. Schmitt-trigger action at all inputs makes the circuit

tolerant of slower input rise and fall times. This device ensures very low static and dynamic power

consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for

partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

? Automotive product qualification in accordance with AEC-Q100 (Grade 1)

? Specified from -40 °C to +85 °C and from -40 °C to +125 °C

? Wide supply voltage range from 0.8 V to 3.6 V

? CMOS low power dissipation

? High noise immunity

? Overvoltage tolerant inputs to 3.6 V

? Low noise overshoot and undershoot < 10 of VCC

? IOFF circuitry provides partial power-down mode operation

? Latch-up performance exceeds 100 mA per JESD 78 Class II

? Low static power consumption; ICC = 0.9 μA (maximum)

? Complies with JEDEC standards:

? JESD8-12 (0.8 V to 1.3 V)

? JESD8-11 (0.9 V to 1.65 V)

? JESD8-7 (1.65 V to 1.95 V)

? JESD8-5 (2.3 V to 2.7 V)

? JESD8C (2.7 V to 3.6 V)

? ESD protection:

? MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V

? HBM JESD22-A114F Class 3A. Exceeds 5000 V

? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

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