描述 Description

The ZL30693 offers three channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment.? Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.

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Under the same family, the?ZL3066x?offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for line card interface. Also available is?ZL3079x?that support?one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms.

特性 Features

Three independent clock channels
Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
Ultra-fast lock to GPS/GNSS and 1PPS for faster power-up time for 4G LTE, 5G & Wireless Infrastructure
Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
Split oscillator option lowers cost, lowers jitter, and provides redundancy
Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
Excellent jitter performance of Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
Up to three programmable digital PLLs/NCOs with loop bandwidth from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
Accepts up to 10 differential or 10 single ended input references
Full reference monitoring of electrical failures
Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
Easy Configuration and dynamic programming via SPI/I2C interface
Factory programming available
Operates from a single crystal resonator or clock oscillator
Applications/Uses
? Central timing function for carrier network equipment compliant to ITU-T G.8262, G.8273.2, G.8273.4
? Communications systems timed by any combination of Synchronous Ethernet, IEEE 1588 PTP, or GPS/GNSS
? 5G wireless CU, DU, and RU systems
? 5G systems with precise time requirements driven by advanced services such as carrier aggregation, coordinated multipoint, OTDOA location, etc.
? Integrated basestation reference clock for 2G through 4G LTE-A macro and micro cells
? Carrier routers, access aggregation, wireless backhaul
? SONET/SDH systems

簡介

ZL30693屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由制造生產(chǎn)的ZL30693應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。