描述 Description

The ZL30671 offers one channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment.? Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.

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特性 Features

? Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
? Ultra-fast lock to GPS/GNSS and 1PPS for faster power-up time for 4G LTE, 5G & Wireless Infrastructure
? Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
? Split oscillator option lowers cost, lowers jitter, and provides redundancy
? Fully compliant to EEC (G.8262), SEC (G.813), GR-253 SMC and GR-1244 Stratum 3/3E
? Excellent jitter performance of

簡介

ZL30671屬于集成電路（IC）的應(yīng)用特定時鐘/定時。由制造生產(chǎn)的ZL30671應(yīng)用特定時鐘/定時專用時鐘和計時 IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。