描述 Description

The W634GG6NB is a 4G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J

特性 Features

Double Data Rate architecture: two data transfers per clock cycle Eight internal banks for concurrent operation8 bit prefetch architectureCAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14Burst Length 8(BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF)Programmable read burst ordering: interleaved or nibble sequentialBi-directional, differential data strobes (DQS and /DQS# ) are transmitted / received with dataEdge-aligned with Read data and center-aligned with Write dataDLL aligns DQ and DQS transitions with clockDifferential clock inputs (CK and /CK# )Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate) Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiencyRead Latency = Additive Latency plus CAS Latency (RL = AL + CL)Auto-precharge operation for read and write burstsRefresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)Precharged Power Down and Active Power DownData masks (DM) for write dataProgrammable CAS Write Latency (CWL) per operating frequencyWrite Latency WL = AL + CWLMulti purpose register (MPR) for readout a predefined system timing calibration bit sequenceSystem level timing calibration support via write leveling and MPR read patternZQ Calibration for output driver and ODT using external reference resistor to groundAsynchronous RESET# pin for Power-up initialization sequence and reset functionProgrammable on-die termination (ODT) for data, data mask and differential strobe pairsDynamic ODT mode for improved signal integrity and preselectable termination impedances during writes 2K Byte page size Interface: SSTL_15