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W632GG8KB

雙倍數(shù)據(jù)傳輸速率同步動(dòng)態(tài)隨機(jī)存取內(nèi)存-3rd generation(第三代); ?Power Supply: VDD, VDDQ = 1.5 V ± 0.075 V \n? Double Data Rate architecture: two data transfers per clock cycle \n? Eight internal banks for concurrent operation \n? 8 bit prefetch architecture \n? CAS Latency: 6, 7, 8, 9, 10, 11 and 13 \n? Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF)\n? Programmable read burst ordering: interleaved or nibble sequential \n? Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data \n? Edge-aligned with read data and center-aligned with write data \n? DLL aligns DQ and DQS transitions with clock \n? Differential clock inputs (CK and CK#) \n? Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate) \n? Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency \n? Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) \n? Auto-precharge operation for read and write bursts \n? Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) \n? Precharged Power Down and Active Power Down \n? Data masks (DM) for write data \n? Programmable CAS Write Latency (CWL) per operating frequency \n? Write Latency WL = AL + CWL \n? Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence \n? System level timing calibration support via write leveling and MPR read pattern \n? ZQ Calibration for output driver and ODT using external reference resistor to ground \n? Asynchronous RESET# pin for Power-up initialization sequence and reset function \n? Programmable on-die termination (ODT) for data, data mask and differential strobe pairs \n? Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes \n? 1K Byte page size \n? Interface: SSTL_15\n? Package:WBGA78 Ball (8x10.5mm2), RoHS compliant;

The W632GG8KB is a 2G bits DDR3 SDRAM and speed involving -11, -12/12I and -15/15I\n

W632GG8KB

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB-11

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB-12

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB12I

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB-15

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB15I

32M X 8 BANKS X 8 BIT DDR3 SDRAM

W632GG8KB-11

Package：78-TFBGA；包裝：托盤(pán) 類(lèi)別：集成電路（IC） 存儲(chǔ)器 描述：IC DRAM 2GBIT PARALLEL 78WBGA

ETC

W632GG8KB-11 TR

Package：78-TFBGA；包裝：管件 類(lèi)別：集成電路（IC） 存儲(chǔ)器 描述：IC DRAM 2GBIT PARALLEL 78WBGA

ETC

W632GG8KB-12

Package：78-TFBGA；包裝：托盤(pán) 類(lèi)別：集成電路（IC） 存儲(chǔ)器 描述：IC DRAM 2GBIT PARALLEL 78WBGA

ETC