描述 Description

The V62C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three state outputs are TTL compatible and allow for
direct interfacing with common system bus structures.

特性 Features

■High-speed: 35, 70 ns
■Ultra low DC operating current of 5mA (max.)
■Low Power Dissipation:
– TTL Standby: 3 mA (Max.)
– CMOS Standby: 20 μA (Max.)
■Fully static operation
■All inputs and outputs directly compatible
■Three state outputs
■Ultra low data retention current (VCC= 2V)
■Single 5V ±10% Power Supply
■Packages
– 28-pin TSOP (Standard)
– 28-pin 600 mil PDIP
– 28-pin 330 mil SOP (450 mil pin-to-pin)