描述 Description

The V62C5181024 is a 1,048,576-bit random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELICs high performance CMOS process. Inputs and tree-state outputs are TTL compatible and allow for circuit interfacing with common system bus structures.

特性 Features

■ High-speed: 35, 45, 55, 70 ns

■ Ultra low DC operating current of 20mA (max.)

TTL Standby: 4mA (Max.)

CMOS Standby: 60μA (Max.)

■ Fully static operation

■ All inputs and outputs directly compatible

■ Three state outputs

■ Ultra low datat retention current(VCC = 2V)

■ Single 5V ± 10 Power Supply