首頁(yè)>V62/18602-01XB>規(guī)格書(shū)詳情
V62/18602-01XB中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

廠(chǎng)商型號(hào) |
V62/18602-01XB |
功能描述 | LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner |
絲印標(biāo)識(shí) | |
封裝外殼 | WQFN |
文件大小 |
1.76875 Mbytes |
頁(yè)面數(shù)量 |
102 頁(yè) |
生產(chǎn)廠(chǎng)商 | TI |
中文名稱(chēng) | 德州儀器 |
網(wǎng)址 | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-8-8 17:05:00 |
人工找貨 | V62/18602-01XB價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
V62/18602-01XB規(guī)格書(shū)詳情
1 Features
1? EP Features
– Gold Bondwires
– Temperature Range: –55 to +105 °C
– Lead Finish SnPb
? Maximum Distribution Frequency: 3.2 GHz
? JESD204B Support
? Ultra-Low RMS Jitter
– 88-fs RMS Jitter (12 kHz to 20 MHz)
– 91-fs RMS Jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
? Up to 14 Differential Device Clocks From PLL2
– Up to 7 SYSREF Clocks
– Maximum Clock Output Frequency 3.2 GHz
– LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs From PLL2
? Up to 1 Buffered VCXO/Crystal Output From PLL1
– LVPECL, LVDS, 2xLVCMOS Programmable
? Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
? Dual Loop PLLatinum? PLL Architecture
? PLL1
– Up to 3 Redundant Input Clocks
– Automatic and Manual Switchover Modes
– Hitless Switching and LOS
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode When Input Clocks are Lost
? PLL2
– Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-Doubler
– Two Integrated Low-Noise VCOs
? 50 Duty Cycle Output Divides, 1 to 32
(Even and Odd)
? Precision Digital Delay, Dynamically Adjustable
? 25-ps Step Analog Delay
? 3.15-V to 3.45-V Operation
? Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8
mm)
2 Applications
? Wireless Infrastructure
? Data Converter Clocking
? Networking, SONET/SDH, DSLAM
? Medical / Video / Military / Aerospace
? Test and Measurement
3 Description
The LMK04828-EP device is the industry's highest
performance clock conditioner with JESD204B
support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as highperformance
outputs for traditional clocking systems.
The high performance combined with features like the
ability to trade off between power or performance,
dual VCOs, dynamic digital delay, holdover, and
glitchless analog delay make the LMK04828-EP ideal
for providing flexible high-performance clocking trees.
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
25+ |
LQFP (PN) |
6000 |
原廠(chǎng)原裝,價(jià)格優(yōu)勢(shì) |
詢(xún)價(jià) | ||
TI/德州儀器 |
23+ |
TSSOP8 |
11200 |
原廠(chǎng)授權(quán)一級(jí)代理、全球訂貨優(yōu)勢(shì)渠道、可提供一站式BO |
詢(xún)價(jià) | ||
TI/德州儀器 |
25+ |
原廠(chǎng)封裝 |
10280 |
原廠(chǎng)授權(quán)代理,專(zhuān)注軍工、汽車(chē)、醫(yī)療、工業(yè)、新能源! |
詢(xún)價(jià) | ||
Texas Instruments |
23+/24+ |
SOT-223-6 |
8600 |
只供原裝進(jìn)口公司現(xiàn)貨+可訂貨 |
詢(xún)價(jià) | ||
TI/德州儀器 |
25+ |
原廠(chǎng)封裝 |
9999 |
詢(xún)價(jià) | |||
TI/德州儀器 |
25+ |
原廠(chǎng)封裝 |
10280 |
詢(xún)價(jià) | |||
TI |
22+ |
NA |
500000 |
萬(wàn)三科技,秉承原裝,購(gòu)芯無(wú)憂(yōu) |
詢(xún)價(jià) | ||
TI/德州儀器 |
25+ |
原廠(chǎng)封裝 |
10280 |
詢(xún)價(jià) | |||
N/A |
99 |
詢(xún)價(jià) | |||||
TI |
24+ |
con |
35960 |
查現(xiàn)貨到京北通宇商城 |
詢(xún)價(jià) |