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UPD720133

MOS Integrated Circuit

TheμPD720133isdesignedtofunctionasabridgebetweenUSB2.0andATA/ATAPI.TheμPD720133complieswiththeUniversalSerialBusSpecificationRevision2.0full-/high-speedsignalingandworksupto480Mbps.TheμPD720133consistsofaCISCprocessor,anATA/ATAPIcontroller,anendpointcon

UPD720133

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate12/480Mbps) ?CompliantwithATA/ATAPI-6(LBA48,PIOMode0-4,MultiWordDMAMode0-2,UltraDMAMode0-4) ?USB2.0high-speedbuspowereddevicecapability ?CertifiedbyUSBimplementersforumandgranted

UPD720133

USB2.0 to IDE Bridge; ? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)\n? Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)\n? USB2.0 high-speed bus powered device capability\n? Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID: 40001985)\n? One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver\n? USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)\n? Automatic chirp assertion and full-/high-speed mode change\n? USB Reset, Suspend and Resume signaling detection\n? Supports power control functionality for IDE device as CD-ROM and HDD\n? Supports set feature (TEST_MODE) functionality\n? System Clock is generated by 30 MHz X’tal\n? 2.5 V and 3.3 V power supply;

The μPD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The μPD720133 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The μPD720133 consists of a CISC processor, an ATA/ATAPI controller, an endpoint controller (EPC), a serial interface engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protocols (bulk only protocol) are handled by the USB2.0 transceiver, the SIE and the EPC. The V30MZ CISC processor in the μPD720133 takes care of the activities in the transport layer. The firmware controlling the μPD720133 is located in an embedded ROM.FEATURES\n? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)\n? Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)\n? USB2.0 high-speed bus powered device capability\n? Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID: 40001985)\n? One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver\n? USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)\n? Automatic chirp assertion and full-/high-speed mode change\n? USB Reset, Suspend and Resume signaling detection\n? Supports power control functionality for IDE device as CD-ROM and HDD\n? Supports set feature (TEST_MODE) functionality\n? System Clock is generated by 30 MHz X’tal\n? 2.5 V and 3.3 V power supply