UCC3808APW-2屬于集成電路（IC）的PMIC-穩(wěn)壓器-DCDC開關(guān)式控制器。由美國(guó)德州儀器公司制造生產(chǎn)的UCC3808APW-2DC-DC 開關(guān)控制器PMIC（電源管理集成電路）DC 到 DC 開關(guān)式控制器是用于高效率電路的穩(wěn)壓 IC，其配置為生成高于（突升或步升）或低于（突降或步降）輸入電源的輸出電源電壓。其他拓?fù)浣Y(jié)構(gòu)可能包括：降壓-升壓、反激、正激、Cuk、SEPIC、全橋、半橋和推挽式。這些器件不同于需要最小電壓并“燒盡”多余電壓的線性穩(wěn)壓器。

1 Features

1? Dual-Output Drive Stages in Push-Pull

Configuration

? Current-Sense Discharge Transistor to Improve

Dynamic Response

? 130-μA Typical Starting Current

? 1-mA Typical Run Current

? Operation to 1 MHz

? Internal Soft Start

? On-Chip Error Amplifier With 2-MHz Gain

Bandwidth Product

? On-Chip VDD Clamping

? Output Drive Stages Capable of 500-mA Peak-

Source Current, 1-A Peak-Sink Current

2 Applications

? High-Efficiency Switch-Mode Power Supplies

? Telecom DC-to-DC Converters

? Point-of-Load Power Modules

? Low-Cost Push-Pull and Half-Bridge Applications

3 Description

The UCCx808A devices are a family of BiCMOS

push-pull, high-speed, low-power, pulse-width

modulators. The UCCx808A contains all of the control

and drive circuitry required for off-line or DC-to-DC

fixed frequency current-mode switching power

supplies with minimal external parts count.

The UCCx808A dual-output drive stages are

arranged in a push-pull configuration. Both outputs

switch at half the oscillator frequency using a toggle

flip-flop. The dead time between the two outputs is

typically 60 ns to 200 ns depending on the values of

the timing capacitor and resistors, thus limiting each

output stage duty cycle to less than 50%.

The UCCx808A family offers a variety of package

options, temperature range options, and choice of

undervoltage lockout levels. The family has UVLO

thresholds and hysteresis options for off-line and

battery-powered systems.

The UCCx808A is an enhanced version of the

UCC3808 family. The significant difference is that the

A versions feature an internal discharge transistor

from the CS pin to ground, which is activated each

clock cycle during the oscillator dead time. The

feature discharges any filter capacitance on the CS

pin during each cycle and helps minimize filter

capacitor values and current sense delay.