UCC2808AQDR-2EP屬于集成電路（IC）的PMIC-穩(wěn)壓器-DCDC開關(guān)式控制器。由美國德州儀器公司制造生產(chǎn)的UCC2808AQDR-2EPDC-DC 開關(guān)控制器PMIC（電源管理集成電路）DC 到 DC 開關(guān)式控制器是用于高效率電路的穩(wěn)壓 IC，其配置為生成高于（突升或步升）或低于（突降或步降）輸入電源的輸出電源電壓。其他拓撲結(jié)構(gòu)可能包括：降壓-升壓、反激、正激、Cuk、SEPIC、全橋、半橋和推挽式。這些器件不同于需要最小電壓并“燒盡”多余電壓的線性穩(wěn)壓器。

Controlled Baseline

? One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

?40°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product-Change Notification

Qualification Pedigree?

Dual Output Drive Stages in Push-Pull

Configuration

Current Sense Discharge Transistor to

Improve Dynamic Response

130-μA Typical Starting Current

1-mA Typical Run Current

Operation to 1 MHz

Internal Soft Start

On-Chip Error Amplifier With 2-MHz Gain

Bandwidth Product

On Chip VDD Clamping

Output Drive Stages Capable of 500-mA

Peak-Source Current, 1-A Peak-Sink

Current

description/ordering information

The UCC2808A is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The

UCC2808A contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency

current-mode switching power supplies with minimal external parts count.

The UCC2808A dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half

the oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to

200 ns depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle

to less than 50%.

The UCC2808A family offers a variety of package options and choice of undervoltage lockout levels. The family

has UVLO thresholds and hysteresis options for off-line and battery powered systems. Thresholds are shown

in the ordering information table.

The UCC2808A is an enhanced version of the UCC2808 family. The significant difference is that the A versions

feature an internal discharge transistor from the CS pin to ground, which is activated each clock cycle during

the oscillator dead time. The feature discharges any filter capacitance on the CS pin during each cycle and helps

minimize filter capacitor values and current sense delay.