描述 Description

The U74HCT7046 is phase-locked-loop circuit that comprise a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), a lock detector, a common signal input amplifier and a common comparator input. The lock detector capacitor should be connected between pin 15(CLD) and pin 8(GND).For a frequency range of 100kHz to 10MHz,the lock detector capacitor must be 1000pF to 10pF,respectively. The signal can be directly coupled to large voltage signals, or with a series capacitor coupled to small signals. Small voltage signals can be kept within the linear region of the input amplifiers with a self-bias input circuit. The?U74HCT7046?and a passive low-pass filter form a second-order loop PLL. With a linear op-amp, the VCO achieves excellent linearity. The VCO requires external capacitor and resistor. R1 (between R1 and GND) and capacitor C1 (between C1A and C1B) determine the frequency range of the VCO. R2 (between R2 and GND) enables the VCO to have a frequency offset if required. ?For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, but the DEMOUT voltage of U74HCT7046 equals the VCO input voltage. When DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input (COMPIN). If the VCO input is held at?a constant DC level, the VCO output signal has a duty factor of 50% (maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption.