描述 Description

The TUSB6250 is a USB 2.0 HS-capable function controller with an integrated UTMI compliant PHY. The TUSB6250 is intended as a USB 2.0 to ATA/ATAPI bridge for storage devices using a standard ATA or ATAPI interface.
The TUSB6250 is designed to utilize both the fast performance of the state machine and the programmability and flexibility of the embedded microcontroller and firmware. With the elaborative balance between the microcontroller unit (MCU) and the state machine, in addition to its embedded fast MCU (up to 30 MIPS), eight configurable endpoints, up to 40K bytes of configurable code, and data buffer SRAM, the TUSB6250 provides a bridge solution to meet both the performance and flexibility requirement of the next generation external storage devices. With the a low power consumption USB 2.0 integrated PHY, the TUSB6250 also enables the true USB 2.0 high-speed bus-powered application.

特性 Features

? Universal Serial Bus (USB)
- Fully compliant with USB 2.0 specification: TID #40390418
? Integrated USB 2.0 UTMI compliant transceiver (PHY)
? Supports USB high speed (HS, 480 Mbits/sec) and full speed (FS, 12 Mbits/sec)
? Supports USB suspend/resume and remote wake-up operation
? Supports USB device-unique serial number by using on-chip unique die ID
? Supports eight configurable endpoints (four input and four output) with a user-programmable buffer size, in addition to the default control endpoint (endpoint 0):
- Each endpoint can be configured for interrupt and bulk (double buffered) transfers.
? All endpoints share the 4K byte data buffer implemented in the SPRAM (single port SRAM).

? Microcontroller Unit (MCU)
- Integrated 60-MHz 8051 microcontroller with two clocks per cycle (up to 30 MIPS)
? Application code is loadable from either the USB host or the external EEPROM (via the I2C interface)
? 8K bytes of ROM for the boot loader
? 1152 bytes of RAM with multiple bank selectable capability for the internal data buffer (IDATA space)
? 40K bytes of RAM, configurable for either code or data space, which provides flexibility to the end product application:
- 32K byte code RAM with 8K byte sector buffer data space
? 16K byte code RAM with 24K byte sector buffer data space
? 8K byte code RAM with 32K byte sector buffer data space
? Master I2C interface controller for external device accesses capable of 100 Kbits/sec or 400 Kbits/sec transfer speed.
? Up to 13 GPIOs and three general-purpose open-drain outputs can be used for end product specific functions.
? ATA/ATAPI Interface Controller
- Supports USB mass storage device class specification bulk-only transfer protocol
? Glueless interface to ATA and ATAPI drives with full ATA and ATAPI protocol support
? High-performance DMA engine supports all PIO, multiword DMA, and UDMA transfer modes up to UDMA mode 4 (UDMA-66 or ATA-66).
? Correctly handles all 13 cases in bulk-only transfer protocol under all supported transfer modes.
? Fully programmable ATA/ATAPI interface access timing
? Provides multiple flexible transfer options to achieve both high-speed transfer by the state machine and high flexibility with MCU involvement:
- Fully-manual transfer (both command and data) by the MCU
? Semi-auto transfer with command transfer by the MCU and data transfer by the state machine
? High-performance fully-auto data transfer mainly by the state machine with few MCU involvements.
? Supports mass-storage devices compatible with the ATA/ATAPI-5 specification:
- Hard-disk drive
? DVD/CD-ROM
? CD-R/W, DVD-R/W
? Compact flash
? PCMCIA type II card or hard drive
? MO drive
? Dual drive support
- Capable of supporting one master and one slave drive in any combination of ATA and ATAPI.
? Provides easy control to put the ATA/ATAPI bus into a 3-state condition through one register bit setting.
? 5-V failsafe I/Os for the ATA/ATAPI interface
? General Features
- Operates on a 24-MHz external crystal with on-chip APLL
? Low-power mode (compliant with bus power requirement of