1 Features

? Input voltage range: 4.5 V to 17 V

? Output voltage range: 0.25 V to 5.5 V

? Dual output supporting N+M ≤ 12 phases, M ≤ 6

phases

? Native trans-inductor voltage regulator (TLVR)

topology support

? AMD? SVI3 compliant

? Enhanced D-CAP+? control to provide superior

transient performance with excellent dynamic

current sharing

? Programmable loop compensations

? Flexible phase-firing sequencing

? Individual phase current calibrations and reports

? Dynamic phase shedding with programmable

current threshold for optimizing efficiency at light

and heavy loads

? Fast phase-adding for undershoot reduction

? Driverless configuration for efficient high-frequency

switching

? Fully compatible with TI NexFET? power stages

for high-density solutions

? Accurate, adjustable voltage positioning

? Patented AutoBalance? phase current balancing

? Selectable per-phase current limit

? PMBus? system interface for telemetry of voltage,

current, power, temperature, and fault conditions

? 6.00 × 6.00 mm, 48-pin, 0.4 mm pitch, QFN

package

2 Applications

? Rack server

? Microserver and tower server

? High performance computing

? Baseband unit (BBU)

3 Description

The TPS536C5 is a fully AMD SVI3 compliant

step-down controller with dual channels, built-in nonvolatile

memory (NVM), and PMBus? interface,

and is fully compatible with TI NexFET? smart

power stage. Advanced control features such as

D-CAP+? architecture with undershoot reduction

(USR) provide fast transient response, low output

capacitance, and good current sharing. The device

also provides novel phase interleaving strategy and

dynamic phase shedding for efficiency improvement

at different loads. Adjustable control of VCORE slew

rate and voltage positioning round out the AMD

SVI3 features. In addition, the device supports the

PMBus communication interface for reporting the

telemetry of voltage, current, power, temperature, and

fault conditions to the systems. All programmable

parameters can be configured by the PMBus interface

and can be stored in NVM as the new default values

to minimize the external component count.

The TPS536C5 device if offered in a thermally

enhanced 48-pin QFN packaged and is rated to

operate from –40°C to 125°C.