TPIC6A259DW屬于集成電路（IC）的鎖存器。由美國德州儀器公司制造生產(chǎn)的TPIC6A259DW鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

Low rDS(on) . . . 1 Ω Typ

Output Short-Circuit Protection

Avalanche Energy . . . 75 mJ

Eight 350-mA DMOS Outputs

50-V Switching Capability

Four Distinct Function Modes

Low Power Consumption

description

This power logic 8-bit addressable latch controls

open-drain DMOS-transistor outputs and is

designed for general-purpose storage applications

in digital systems. Specific uses include

working registers, serial-holding registers, and

decoders or demultiplexers. This is a multifunctional

device capable of operating as eight

addressable latches or an 8-line demultiplexer

with active-low DMOS outputs. Each open-drain

DMOS transistor features an independent

chopping current-limiting circuit to prevent

damage in the case of a short circuit.

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

as enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS-transistor output inverts the

data input with all unaddressed DMOS-transistor

outputs remaining in their previous states. In the

memory mode, all DMOS-transistor outputs

remain in their previous states and are unaffected

by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latch,

enable G should be held high (inactive) while the

address lines are changing. In the 8-line

demultiplexing mode, the addressed output is

inverted with respect to the D input and all other

outputs are high. In the clear mode, all outputs are

high and unaffected by the address and data

inputs.

Separate power ground (PGND) and logic ground

(LGND) terminals are provided to facilitate

maximum system flexibility. All PGND terminals

are internally connected, and each PGND

terminal must be externally connected to the

power system ground in order to minimize

parasitic impedance. A single-point connection

between LGND and PGND must be made

externally in a manner that reduces crosstalk

between the logic and load circuits.