TPIC6259DWR屬于集成電路（IC）的鎖存器。由美國德州儀器公司制造生產(chǎn)的TPIC6259DWR鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時(shí)間，保持的邏輯狀態(tài)都可以改變。“透明”鎖存器還允許設(shè)備輸出在鎖存使能信號有效時(shí)反映輸入的當(dāng)前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時(shí)改變。

Low rDS(on) . . . 1.3 Ω Typical

Avalanche Energy . . . 75 mJ

Eight Power DMOS Transistor Outputs of

250-mA Continuous Current

1.5-A Pulsed Current Per Output

Output Clamp Voltage at 45 V

Four Distinct Function Modes

Low Power Consumption

description

This power logic 8-bit addressable latch controls

open-drain DMOS transistor outputs and is

designed for general-purpose storage applications

in digital systems. Specific uses include

working registers, serial-holding registers, and

decoders or demultiplexers. This is a multifunctional

device capable of storing single-line

data in eight addressable latches with 3-to-8

decoding or demultiplexing mode active-low

DMOS outputs.

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

as enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS transistor output inverts the

data input with all unaddressed DMOS-transistor

outputs remaining in their previous states. In the

memory mode, all DMOS-transistor outputs

remain in their previous states and are unaffected

by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latch,

enable G should be held high (inactive) while the

address lines are changing. In the 3-to-8 decoding

or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are

high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,

and 20 are internally connected, and each pin must be externally connected to the power system ground in order

to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,

11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the

logic and load circuits.

The TPIC6259 is characterized for operation over the operating case temperature range of –40°C to 125°C.