THS8135PHPG4屬于集成電路（IC）的ADC/DAC-特殊用途。由美國德州儀器公司制造生產(chǎn)的THS8135PHPG4ADC/DAC - 特殊用途該產(chǎn)品族中的產(chǎn)品可用于模擬和數(shù)字表示的信息轉(zhuǎn)換，適用于特定用例，或集成了通用數(shù)據(jù)轉(zhuǎn)換器中不常見的其他功能。例如針對超聲或汽車雷達應用集成了低噪聲放大器和可變增益級的器件、注重音頻和視頻的產(chǎn)品、在段碼式顯示器上集成顯示測量值功能的器件、集成輸入輸出電氣隔離的器件等。

1FEATURES

2? Triple 10-Bit D/A Converters

? 240-MSPS Operation

? YPbPr/RGB Configurable Blanking Levels,

Correctly Positioned for Either Full (0-1023) or

Video (ITU-R.BT601) Compliant Input Code

Ranges

? Generic Triple DAC Mode for Non-Video

Applications

? Direct Drive of Double-Terminated 75-Ω Load

Into Standard Video Levels

? 3x10 Bit 4:4:4, 2x10 Bit 4:2:2 or 1x10 Bit 4:2:2

(ITU-R.BT656) Multiplexed YCbCr/GBR Input

Data Formats

? Bi-Level (EIA) or Tri-Level (SMPTE) Sync

Generation

? Integrated Sync-On-Green/Luminance or Sync-

On-All Composite Sync Insertion

? Internal Voltage Reference

? Low-Power Operation From 3.3-V Analog and

1.8-V Digital Suply Levels

APPLICATIONS

? High-Definition Television (HDTV) Set-Top

Boxes/Receivers/Displays

? High-Resolution Image Processing

DESCRIPTION

The THS8135 is a general-purpose triple high-speed D/A converter optimized for use in video/graphics

applications. The device operates from 3.3-V analog and 1.8-V digital supplies. The THS8135 performance is

assured at a sampling rate up to 240 MSPS. The THS8135 consists of three 10-bit D/A converters and additional

circuitry for bi-level/tri-level sync and blanking level generation. By providing a dc offset for the lowest video

amplitude output in video DAC mode, the device can insert a (negative) bi-level or (negative/positive) tri-level

sync on either only the green/luminance (sync-on-green/sync-on-Y) channel or on all channels for video

applications. A generic DAC mode avoids this dc offset, making this device suitable for non-video applications as

well.

The THS8135 is a footprint-compatible functional upgrade to the THS8133. In addition, the THS8135 allows a

higher update rate for oversampled video digitizing for all PC graphics formats up to UXGA (1600x1200)

resolution at 85 Hz and all practical digital TV formats including HDTV. The support for oversampling significantly

reduces the complexity of the analog reconstruction filter required behind the DAC.

Standard video levels can be generated for the full 10-bit input code range. Alternatively, the same levels can be

reached from a reduced input code range compliant to the video sampling standard ITU-R.BT-601. In that case,

the full-scale range of the DAC is dependent on the RGB or YCbCr color space configuration of the device.

When configured for RGB operation, full video output swing is reached for input codes 64-940 on all channels.

When configured for YCbCr operation, code range 64-940 on Y and code range 64-960 on Cb and Cr channels

generate full output swing using internal amplitude scaling on these color components. The device provides

headroom to accommodate under-/over-shoot outside the ITU-R.BT601 range to allow the generation of ITUR.

BT601 illegal colors or super-black / super-white levels.

A digital control input for insertion of a reference (blanking) level on the analog outputs is included. The

amplitude of the blanking level is configurable for either RGB or YPbPr component outputs and for full or reduced

input code ranges. The inserted sync output amplitude(s) always has the required 7:3 ratio to the full-scale video

amplitude.

The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device

provides a flexible configuration of maximum output current drive. The devices output drivers have been

specifically designed to produce standard video output levels when directly connected to a single-ended doubleterminated

75-Ω coaxial cable.

The input data format can be either 3x10 bit 4:4:4, 2x10 bit 4:2:2, or 1x10 bit 4:2:2. This enables a direct

interface to a wide range of video DSP/ASICs including parts generating ITU-R.BT656 formatted output data.

However, the THS8135 needs specific input synchronization signals to properly insert a composite sync onto its

outputs as it does not extract embedded SAV/EAV synchronization codes from the ITU-R.BT656 input. Along

with other extra functionality, this feature is available on a derivative device (THS8200).