Application Information

The TAMC651 is a double Mid-Size or Full-Size AMC.1 Type 1 module according to MTCA.4 (MicroTCA Enhancements for Rear I/O and Precision Timing) and provides a user configurable Spartan-6 FPGA (XC6SLX45T-2 or XC6SLX100T-2).

The Spartan-6’s integrated PCIe Endpoint Block is connected to AMC port 4.

AMC ports 12-15 (point-to-point) and AMC ports 17-20 (multi-drop) connect to FPGA I/O pins via on-board M-LVDS transceivers.

One of the Spartan-6 GTP transceiver utilizes an SFP interface available at the front plate. SFP support signals are available as FPGA I/O pins. Four FPGA controlled LEDs are also available at the front plate.

According to MTCA.4, the TAMC651 provides two 30-pair ADF connectors at the Zone 3 interface (Rear I/O).

The following I/O signals are available at the Zone 3 interface: 46 differential FPGA I/O lines (LVDS), 2 differential reference clock lines (LVDS), 2 Spartan-6 GTP transceivers. The differential FPGA I/O lines could also be used as single-ended I/O lines (FPGA bank supply for the Zone 3 I/O signals is 2.5V).

The TAMC651 provides a 128 Mbyte, 16 bit wide DDR3 SDRAM bank. The SDRAM-interface utilizes one of the internal hardwired Memory Controller Blocks of the Spartan-6 FPGA.

The FPGA is configured via a Xilinx platform flash which is programmable via a JTAG header. The JTAG header also supports readback and on-chip debugging of the FPGA design (e.g. using Xilinx “ChipScope”). A serial SPI-Flash can be used as alternative configuration data source or for user data storage.

The TAMC651 is shipped with blank configuration devices.

A programmable clock generator supplies differential clock lines to FPGA global clock pins, to an on-board clock crosspoint-switch and to the Spartan-6 GTP transceiver used for the SFP interface. The clock generator is programmable by the FPGA design.

The TAMC651 also provides a configurable clock crosspoint-switch. Clock inputs are: programmable clock generator output, FPGA clock output, AMC TCLKA and TCLKB. Two clock outputs are connected to FPGA global clock pins and two clock outputs are available as reference clocks at the Zone 3 interface.

User applications for the TAMC651 options with the XC6SLX45T-2 FPGA can be developed using the ISE WebPACK design software, which is available free of charge from www.xilinx.com. TAMC651 options with the XC6SLX100T-2 require a full licensed ISE Design Suite.

TEWS offers an FPGA Development Kit (TAMC651-FDK) which consists of a well documented basic example design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers certain functionalities of the TAMC651. It implements a DMA capable PCIe endpoint with interrupt support, register mapping and DDR3 memory access. It comes as a Xilinx ISE project with source code and as a ready-to-download bitstream.