描述 Description

The SY89826L is a precision fanout buffer with 22 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL pin. The OE (Output Enable) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89826L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89826L is available in a single space saving package, enabling a lower overall cost solution.

特性 Features

? High-performance, 1GHz LVDS fanout buffer/ translator
? 22 differential LVDS output pairs
? Guaranteed AC parameters over temperature and voltage:
? >1GHz fMAX
? <50ps within device skew
? <400ps tr/tf?time
? Low jitter performance
? <1psrms?cycle-to-cycle jitter
? <1ps (pk-pk) total jitter
? 2:1 mux input accepts LVDS and LVPECL
? 3.3V supply voltage
? LVDS input includes internal 100Ω termination
? Output enable function
? Available in a 64-Pin EPAD-TQFP

簡介

SY89826L屬于集成電路（IC）的時鐘緩沖器驅動器。由制造生產(chǎn)的SY89826L時鐘緩沖器，驅動器時鐘緩沖器和驅動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅動負載的影響而從某個信號源復制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進行所用電信號格式轉換。