描述 Description

The SY89113U is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom and enterprise server distribution applications. The input includes a 2:1 MUX for clock switchover applications. Unlike other multiplexers, this input includes a unique isolation design that minimizes channel-to-channel crosstalk. The SY89113U distributes clock frequencies from DC to >1GHz guaranteed over temperature and voltage. The SY89113U incorporates a synchronous output enable (EN) so that the outputs will only be enabled/disabled when they are already in the LOW state.



CLK0 differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path.CLK1 differential input includes a new version of unique, Any-Input architecture that directly interfaces with single-ended TTL/CMOS logic (including 3.3V logic), single-ended LVPECL, differential (AC- or DC-coupled) LVDS, HSTL, CML, and LVPECL logic levels as small as 200mV (400mVPP). CLK1 input requires external termination.LVDS output swing 325mV into 100Ω with extremely fast rise/fall time guaranteed to be less than 250ps.The SY89113U operates from a 2.5V±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89113U is part of Micrel's high-speed, Precision Edge??product line.

特性 Features

? Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies
? Guaranteed AC performance over temperature and voltage:
? DC to >1GHz throughput
? <975ps propagation delay CLK0-to-Q
? <250ps rise/fall time
? <25ps output-to-output skew
? Ultra-low jitter design:
? 130fsRMS?phase jitter (typ.)
? 0.7psRMS?crosstalk-induced jitter
? Unique, patent-pending 2:1 input MUX provides superior isolation to minimize channel-to-channel crosstalk
? CLK0 input features a unique, patent-pending input termination and VT?pin that accepts AC- and DC-coupled inputs (CML, LVPECL, LVDS)
? CLK1 accepts virtually any logic standard:
? Single-ended: TTL/CMOS (including 3.3V logic), LVPECL
? Differential: LVPECL, LVDS, CML, HSTL
? 325mV LVDS-compatible output swing
? Power supply: 2.5V ±5%
? Industrial temperature range -40°C to +85°C
? Available in 44-pin (7mm x 7mm) QFN package

簡(jiǎn)介

SY89113U屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由制造生產(chǎn)的SY89113U時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。