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SY100E136

6-BIT UNIVERSAL UP/DOWN COUNTER

DESCRIPTION TheSY10/100E136are6-bitsynchronous,presettable,cascadableuniversalcounters.Thesedevicesgeneratealook-ahead-carryoutputandacceptalook-ahead-carryinput.ThesetwofeaturesallowforthecascadingofmultipleE136sforwiderbitwidthcountersthatoperateatverynear

SY100E136

6-Bit Universal Up/Down counter; 550MHz count frequency\nExtended 100E VEE?range of –4.2V to –5.5V\nLook-ahead-carry input and output\nFully synchronous up and down counting\nAsynchronous Master Reset\nInternal 75KO input pull-down resistors\nAvailable in 28-pin PLCC package;

The SY10/100E136 are 6-bit synchronous, presettable, cascadable universal counters. These devices generate a look-ahead-carry output and accept a look-ahead-carry input. These two features allow for the cascading of multiple E136s for wider bit width counters that operate at very nearly the same frequency as the stand-alone counter.The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. For more information on utilizing the look-ahead-carry features of the device, please refer to the applications section of this data sheet. The differential COUT output facilitates the E136's use in programmable divider and self-stopping counter applications.Unlike the H136 and other similar universal counter designs, the E136 carry-out and look-ahead-carry-out signals are registered on chip.?This design alleviates the glitch problem seen on many counters where the carryout signals are merely gated. Because of this architecture, there are some minor functional differences between the E136 and H136 counters. The user, regardless of familiarity with the H136, should read this data sheet carefully. Note specifically the operation of the carry-out outputs and the look-aheadcarry- in input when utilizing the Master Reset. When left open, all of the input pins will be pulled LOW via an input pulldown resistor. The Master Reset is an asynchronous signal which, when asserted, will force the Q outputs LOW.The Q outputs need not be terminated for the E136 to function properly. In fact, if these outputs will not be used in a system, it is recommended that they be left open to save power and minimize noise. This practice will minimize switching noise which can reduce the maximum count frequency of the device, or significantly reduce margins against other noise in the system.

SY100E136

6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JC

6-BIT UNIVERSAL UP/DOWN COUNTER

DESCRIPTION TheSY10/100E136are6-bitsynchronous,presettable,cascadableuniversalcounters.Thesedevicesgeneratealook-ahead-carryoutputandacceptalook-ahead-carryinput.ThesetwofeaturesallowforthecascadingofmultipleE136sforwiderbitwidthcountersthatoperateatverynear

SY100E136JCTR

6-BIT UNIVERSAL UP/DOWN COUNTER

DESCRIPTION TheSY10/100E136are6-bitsynchronous,presettable,cascadableuniversalcounters.Thesedevicesgeneratealook-ahead-carryoutputandacceptalook-ahead-carryinput.ThesetwofeaturesallowforthecascadingofmultipleE136sforwiderbitwidthcountersthatoperateatverynear

SY100E136JC

6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JCTR

6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JZ

6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JZTR

6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JC-TR

Package：28-LCC（J 形引線）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC COUNTER UP/DOWN 6-BIT 28-PLCC