描述 Description

The Smart Reset? devices provide a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing extended Smart Reset? input delay time (tSRC) and combined push-button inputs, which together ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push-buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time tSRCcauses a hard reset of the processor through the reset output.

The STM6524 has two combined delayed Smart Reset? inputs (SR0,SR1) with preset delayed Smart Reset? setup time (tSRC). The reset output is asserted after both of the Smart Reset? inputs were held active for the selected tSRCdelay time. Depending on selected option theRSToutput remains asserted either until at least oneSRinput goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC(i.e. factory-programmed). The reset output,RST, is active low or active high, push-pull or open drain with optional pull-up resistor. The device fully operates over a broad VCCrange 1.65 V to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the deasserted reset output levels are then valid down to 1.0 V.

特性 Features

? Operating voltage 1.65 V to 5.5 V
? Low supply current 1.5 μA
? Integrated test mode
? Dual Smart Reset? push-button inputs with fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal pull-up resistor
? Push-button controlled reset pulse duration
?Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed
?Option 2: defined output reset pulse duration (tREC), factory-programmed
? No power-on reset
? Single reset output
?Active low or active high
?Push-pull or open drain with optional pull-up resistor
? Fixed Smart Reset? input logic voltage levels
? Operating temperature: –40 C to +85 C
? UDFN6 package: 1.6 mm x 1.3 mm
? ECOPACK?2 (RoHS compliant, Halogen-Free)

簡介

STM6524屬于集成電路（IC）的監(jiān)控器。由制造生產(chǎn)的STM6524監(jiān)控器PMIC 監(jiān)控器用于監(jiān)視和/或控制電路中的電壓軌，能夠連接微控制器以維持一定的功率限值。監(jiān)控器類型包括電池備用電路、監(jiān)控器、多電壓監(jiān)控器、電源監(jiān)控器、穩(wěn)壓器/監(jiān)控器、復(fù)位計時器、定序器、簡單復(fù)位/上電復(fù)位、智能開/關(guān)控制器、系統(tǒng)管理器、電壓檢測器和看門狗電路。