STLVDS32BDR屬于集成電路（IC）的驅(qū)動(dòng)器接收器收發(fā)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的STLVDS32BDR驅(qū)動(dòng)器，接收器，收發(fā)器該系列產(chǎn)品的主要功能是提供必需的硬件資源，以通過延長(zhǎng)電纜或印制線進(jìn)行通信。確切的功能會(huì)因所采用的通信協(xié)議而異，可能包括諸如瞬態(tài)抑制之類的功能，這些功能對(duì)于通信用途可能并非絕對(duì)必要，但對(duì)于可能的使用環(huán)境卻是明智之選。

描述 Description

The STLVDS32 is a differential line receiver that implements the electrical characteristics of low voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5 V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds and allow operations with a 3.3 V supply rail. This differential receiver provides a valid logical output state with a 3.3 V supply rail. It also provides a valid logical output state with a ±100 mV differential input voltage within the input common mode voltage range. The input common mode voltage allows 1 V of ground potential difference between two LVDS nodes.

The intended application of this device and signalling technique is both point-to-point and multidrop data transmission over controlled impedance media approximately 100 Ω. The transmission media may be printed circuit board traces, backplanes or cables. The ultimate rate and distance of data transfer depend upon the attenuation characteristics of the media and noise coupling to the environment.

The STLVDS32 version is characterized for operation from -55°C to 125°C.

特性 Features

■ Meets or exceeds the requirements of ansi

TIA/EIA-644 standard

■ Operates with a single 3.3 V supply

■ Designed for signaling rate up to 400 Mbps

■ Differential input thresholds ±100 mV max

■ Typical propagation delay time of 2.5 ns

■ Power dissipation 60 mW typical per receiver

at 200 MHz

■ Low voltage TTL (LVTTL) logic output levels

■ Pin compatible with the AM26LS32,

SN65LVD32

■ Open circuit fail safe

■ ESD protection:

■ 7 kV receiver pins

■ 3 kV all pins vs gnd