STLC5048屬于集成電路（IC）的編解碼器。由意法半導(dǎo)體集團制造生產(chǎn)的STLC5048編解碼器編解碼器是用于通過壓縮和解壓縮來轉(zhuǎn)換數(shù)據(jù)的半導(dǎo)體器件。數(shù)據(jù)壓縮可提高傳輸速度并減少存儲空間。某些編解碼器提供高達 32 位的分辨率，并且分別提供多達 6 個或 8 個模數(shù)轉(zhuǎn)換器和數(shù)模轉(zhuǎn)換器。除三角積分調(diào)制外，還有 I2C、I2S、SPI、串行、HDA、S/DIF、PCM、USB、AC'97 和 SLIMbus 數(shù)據(jù)接口。

DESCRIPTION

The STLC5048 is a monolithic fully programmable 4 channel CODEC and filter. It operates with a single +3.3V supply.

The analog interface is based on a receive output buffer driving the SLIC RX input and on an amplifier input stage normally driven by the SLIC TX output. Due to the single supply voltage a midsupply reference level is generated internally by the device and all analog signals are referred to this level (AGND). The PCM interface uses one common 8KHz frame sync. pulse for transmit and receive direction. The bit clock is automatically detected between four standards: 1.563/1.544MHz, 2.048MHz, 4.096MHz, 8192MHz.

■ FULLY PROGRAMMABLE MONOLITHIC 4 CHANNEL CODEC/FILTER

■ SINGLE +3.3V SUPPLY

■ A/m LAW PROGRAMMABLE

■ LINEAR CODING (16 BITS) OPTION

■ PCM HIGHWAY FORMAT AUTOMATICALLY DETECTED:1.536 or 1.544 MHz2.048, 4.096, 8192 MHz

■ TWO PCM PORTS AVAILABLE

■ TX GAIN PROGRAMMING: 33dB RANGE; <0.01dB STEP

■ RX GAIN PROGRAMMING:42dB RANGE; <0.01dB STEP

■ PROGRAMMABLE SLIC INPUT IMPEDANCE

■ PROGRAMMABLE TRANSHYBRID BALANCE FILTER

■ PROGRAMMABLE EQUALIZATION (FREQUENCY RESPONSE)

■ PROGRAMMABLE TIME SLOT ASSIGNMENT

■ DIGITAL AND ANALOG LOOPBACKS

■ SLIC CONTROL PORTSTATIC (16 I/Os) DYNAMIC (12 I/Os + 4 CS)

■ BUILT-IN TEST MODE WITH TONE GENERATION, MCU ACCESS TO PCM DATA

■ 64 TQFP (10X10mm) PACKAGE

■ PROGRAMMABLE SLIC LINE CURRENT LIMITATION

■ PROGRAMMABLE SLIC OFF-HOOK DETECTION THRESHOLD