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ST31N400數(shù)據(jù)手冊ST中文資料規(guī)格書

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廠商型號

ST31N400

功能描述

ST31 Secure dual interface microcontroller including Biometry features

制造商

ST STMicroelectronics

中文名稱

意法半導體 意法半導體集團

數(shù)據(jù)手冊

下載地址下載地址二

更新時間

2025-8-19 12:00:00

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ST31N400規(guī)格書詳情

描述 Description

Designed for secure ID and banking applications, including biometry, the ST31N600, ST31N500 and ST31N400 devices are serial access microcontrollers that incorporate the most recent generation of Arm? processors for embedded secure systems. The SecurCore? SC000? 32-bit RISC core is built on the Cortex?-M0 core with additional security features to help to protect against advanced forms of attack.

Cadenced at 60?MHz, the SC000? core brings great performance and excellent code density thanks to the Thumb?-2 instruction set.

Some of the devices implement the MIFARE? DESFire? EV3 or MIFARE Plus? EV2 (including MIFARE Classic?) technology.

An RF interface including an RF universal asynchronous receiver (RFUART) enables contactless communication compatible with ISO/IEC?14443 Type A and Type B at up to 848?kbps, and up to 6.8?Mbps with VHBR. It also supports the ISO/IEC?18092 Type F at up to 424?kpbs.

The ST31N platform devices also offer a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1).

Three 16-bit general-purpose timers are available as well as a watchdog timer.

The ST31N platform devices feature hardware accelerators for advanced cryptographic functions. The AES accelerator provides a high-performance implementation of the AES-128, AES-192 and AES-256 algorithms. The 3-key Triple DES accelerator (EDES+) peripheral enables cipher block chaining (CBC) mode, fast DES and triple DES computation based on three key registers and one data register, while the NESCRYPT LLP cryptoprocessor efficiently supports the public key algorithm with native operations up to 4096 bits long.

With their dedicated interface, the ST31N platform devices also support biometry or multiple applications by managing the power supply to external components, and offering an SPI master/slave interface or GPIOs in both contact (via the VCC pad) and contactless (RF harvesting) mode.

The ST31N platform devices operate in the –25 to +85?°C temperature range, in the 2.7?V and 5.5?V supply voltage ranges in contact mode, and complies with ISO/IEC?14443 specification limits. A comprehensive range of power-saving modes enables the design of efficient low-power and contactless applications.



特性 Features

? Hardware features
?Lockstep Arm? SecurCore? SC000? 32-bit core cadenced at up to 60?MHz
?16 Kbytes of user RAM
?Up to 608 Kbytes of secure User high-density Flash memory including 512 bytes of user area:
? 25-year data retention
? 500?000 Erase/Write cycle endurance
? Page Erase time down to 0.8?ms
? Programming performance up to 3?μs/byte in chained mode
? Flash Erase/Write protection programmable on 32-Kbyte sectors

?RF harvesting
?Operating temperature: –25?°C to +85?°C
?Three 16-bit timers with interrupt
?Watchdog timer
?2.7?V to 5.5?V supply voltages
?1.4?V to 2.5?V external power supply generator for biometric components
?External clock frequency up to 10?MHz
?Power-saving Standby state
?Contact assignment compatible with ISO/IEC?7816-3 standards
?Four general-purpose inputs/outputs (GPIOs) and hardware SPI for biometric applications
?ESD protection:
? HBM: 6?kV for ISO pads, 2?kV for GPIO pads and 4?kV and AC0/AC1 contactless pads and GPIO pads
? CDM: 500 V

?IART with RAM buffer for high-speed serial data support (ISO/IEC?78163 T=0/T=1 and EMV? compliant)
?SPI master/slave interface running at up to 6.2?MHz
?I2C software library available at up to 400?kbps
? Contactless features
?Complies with ISO/IEC?14443 Type A and Type B, and ISO/IEC?18092 Type F, with programmable autodetection of Type A, B or F
?35?pF and 68?pF tuning capacitor
?Automatic CPU frequency adaptation for optimum power consumption
?13.56 MHz carrier frequency
?RFUART (RF universal asynchronous receiver transmitter) up to 848?kbps
?Very high bitrate (ASK VHBR) up to 6.8?Mbps in reception and transmission
?1-Kbyte RF frame buffer in dedicated RFUART RAM
?MIFARE Plus? EV2, MIFARE Classic? and MIFARE? DESFire? EV3 hardware and software implementation
?Simultaneous mode (contact and contactless)
? Security features
?SC000 memory protection unit (MPU)
?Active shield
?Library protection unit (LPU)
?Monitoring of environmental parameters, including the temperature detector
?Three-key Triple DES accelerator
?AES accelerator
?AIS-31 Class PTG.2, NIST?SP800-22 and NIST?SP800-90B compliant true random number generator (TRNG)
?NESCRYPT lite low power (LLP) coprocessor for public key cryptography algorithm
?ISO/IEC 13239 calculation block
?Unique serial number on each die
?Highly efficient protection against fault injection
?Protection against multiple attacks
? Targeted certifications
?EMVCo?, CC EAL6+, CUP, FIPS 140-2 compliance (NIST SP800-22 and SP800-90B)

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