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SSTUH32865ET/G

1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications

PhilipsPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

ICSSSTUAF32865A

25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo

IDT

Integrated Device Technology, Inc.

ICSSSTUAF32865A

28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGateENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein160-ballLFBGApackage Applic

RENESASRenesas Technology Corp

瑞薩瑞薩科技有限公司

ICSSSTUAF32865AHLFT

28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Features ?28-bit1:2registeredbufferwithparitycheckfunctionality ?SupportsSSTL_18JEDECspecificationondatainputs andoutputs ?SupportsLVCMOSswitchinglevelsonCSGateENand RESETinputs ?Lowvoltageoperation:VDD=1.7Vto1.9V ?Availablein160-ballLFBGApackage Applic

RENESASRenesas Technology Corp

瑞薩瑞薩科技有限公司

ICSSSTUAF32865AHLFT

25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo

IDT

Integrated Device Technology, Inc.

ICSSSTUAH32865A

25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo

IDT

Integrated Device Technology, Inc.

ICSSSTUAH32865AHLFT

25-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2

Description This28-bit1:2registeredbufferwithparityisdesignedfor1.7Vto1.9VVDDoperation. AllclockanddatainputsarecompatiblewiththeJEDECstandardforSSTL_18.ThecontrolinputsareLVCMOS.Alloutputsare1.8VCMOSdriversthathavebeenoptimizedtodrivetheDDR2DIMMlo

IDT

Integrated Device Technology, Inc.

SSTU32865

1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM

PhilipsPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

SSTU32865EG

1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM

PhilipsPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

SSTU32865ET

1.8V28-bit1:2registeredbufferwithparityforDDR2RDIMM

PhilipsPhilips Semiconductors

飛利浦荷蘭皇家飛利浦

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25+
SOT802
188600
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160-TFBGA
18908
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160-TFBGA(9x13)
56200
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20+
BGA-160
1001
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N智浦
22+
NA
500000
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恩XP
22+
NA
45000
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160TFBGA (9x13)
9000
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恩XP
23+
160-TFBGA
8000
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160-TFBGA
9350
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LFBGA96
3000
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