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SN74LVTH16543DGGR.Z中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

SN74LVTH16543DGGR.Z
廠商型號(hào)

SN74LVTH16543DGGR.Z

功能描述

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件大小

628.11 Kbytes

頁(yè)面數(shù)量

18 頁(yè)

生產(chǎn)廠商

TI2

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-9 11:00:00

人工找貨

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SN74LVTH16543DGGR.Z規(guī)格書(shū)詳情

Members of the Texas Instruments

WidebusE Family

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

Ioff and Power-Up 3-State Support Hot

Insertion

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) VCC operation, but

with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two

8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB

or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and

LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches

in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present

at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA

inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
TI
2025+
SSOP-56
16000
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TI/德州儀器
23+
SSOP56
50000
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詢價(jià)
TI
22+
56SSOP
9000
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TI
SSOP56
68500
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詢價(jià)
TI(德州儀器)
24+
SSOP56300mil
1490
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TI/德州儀器
24+
SSOP
1500
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詢價(jià)
TI/德州儀器
22+
SSOP56
3000
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詢價(jià)
TI
24+
TSSOP-56
90000
一級(jí)代理商進(jìn)口原裝現(xiàn)貨、假一罰十價(jià)格合理
詢價(jià)
22+
NA
3450
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Texas Instruments
24+
56-SSOP
65200
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詢價(jià)