SN74LVCH16541ADLR屬于集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN74LVCH16541ADLR緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進行隔離通信。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· Operates From 1.65 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 4.2 ns at 3.3 V

· Typical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C

· Ioff Supports Partial-Power-Down Mode

Operation

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage

With 3.3-V VCC)

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH16541A is a noninverting 16-bit buffer composed of two 8-bit sections with separate

output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and

2OE2) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the

outputs of that 8-bit buffer section are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.