SN74LVC1G374DCKR屬于集成電路（IC）的觸發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN74LVC1G374DCKR觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

1FEATURES

2? Available in the Texas Instruments NanoStar?

and NanoFree? Packages

? Supports 5-V V CC Operation

? Inputs Accept Voltages to 5.5 V

? Provides Down Translation to VCC

? Max tpd of 4 ns at 3.3 V

? Low Power Consumption, 10-μA Max ICC

? ±24-mA Output Drive at 3.3 V

? Ioff Supports Live Insertion, Partial-Power-

Down Mode, and Back Drive Protection

? Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

? ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION

This single D-type latch is designed for 1.65-V to 5.5-

V VCC operation.

The SN74LVC1G374 features a 3-state output

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer registers,

input/output (I/O) ports, bidirectional bus drivers, and

working registers.

NanoStar? and NanoFree? package technology is

a major breakthrough in IC packaging concepts,

using the die as the package.

On the positive transition of the clock (CLK) input, the

Q output is set to the logic level set up at the data (D)

input.

A buffered output-enable (OE) input can be used to

place the output in either a normal logic state (high or

low logic levels) or the high-impedance state. In the

high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance

state and increased drive provide the capability to

drive bus lines without interface or pullup

components.

OE does not affect the internal operations of the flip-

flop. Old data can be retained or new data can be

entered while the outputs are in the high-impedance

state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow

through the device when it is powered down.