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SN74LVC161284DLR.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

SN74LVC161284DLR.A
廠商型號(hào)

SN74LVC161284DLR.A

功能描述

19-BIT BUS INTERFACE

文件大小

507.73 Kbytes

頁(yè)面數(shù)量

19 頁(yè)

生產(chǎn)廠商 Texas Instruments
企業(yè)簡(jiǎn)稱

TI2德州儀器

中文名稱

美國(guó)德州儀器公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

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更新時(shí)間

2025-8-3 11:16:00

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SN74LVC161284DLR.A規(guī)格書詳情

1.4-kΩ Pullup Resistors Integrated on All

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Designed for the IEEE Std 1284-I (Level 1

Type) and IEEE Std 1284-II (Level 2 Type)

Electrical Specifications

Flow-Through Architecture Optimizes PCB

Layout

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin-Shrink

Small-Outline (DGG) Packages

description/ordering information

The SN74LVC161284 is designed for 3-V to 3.6-V

VCC operation. This device provides

asynchronous two-way communication between

data buses. The control-function implementation

minimizes external timing requirements.

This device has eight bidirectional bits; data can

flow in the A-to-B direction when DIR is high and

in the B-to-A direction when DIR is low. This

device also has five drivers, which drive the cable

side, and four receivers. The SN74LVC161284

has one receiver dedicated to the HOST LOGIC

line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in

a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive

requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel

peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have

a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.

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