Bidirectional Bus Transceivers in

High-Density 20-Pin Packages

Local Bus-Latch Capability

Hysteresis at Bus Inputs Improves

Noise Margins

Choice of True or inverting Logic

Choice of 3-State or Open-Collector

Outputs

DEVICE ouTPuT LoGic

'LS620 3-Stata Inverting

‘L621 Open-Collector True

‘Ls623 3State Tre

description

These octal bus transceivers are designed for asyn-

chronous two-way communication between data

buses. The control function implementation allows

for maximum flexibility in timing.

These devices allow data transmission from the A bus

10 the B bus or from the B bus to the A bus depend-

ing upon the logic levels at the enable inputs (GBA

and GAB).

The enable inputs can be used to disable the device

so that the buses are effectively isolated.

The dual-enable configuration gives the 'LS620,

'L§621, and 'L$623 the capability to store data by

simultaneous enabling of GBA and GAB. Each output

reinforces its Input in this transceiver configuration.

Thus. when both control inputs are enabled and all

other data sources to the two sets of bus lines are at

high impedance, both sets of bus lines (16 in all) will

remain at thair last states. The 8-bit codes appearing

on the two sets of buses will be identical for the

'L§621 and 'LS623 davices or complementary for the

‘LS620.