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SN74LS373

Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output

OctalTransparentLatchwith3-StateOutputs;OctalD-TypeFlip-Flopwith3-StateOutput TheSN74LS373consistsofeightlatcheswith3-stateoutputsforbusorganizedsystemapplications.Theflip-flopsappeartransparenttothedata(datachangesasynchronously)whenLatchEnable(LE)is

SN74LS373

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

ChoiceofEightLatchesorEightD-Type Flip-FlopsinaSinglePackage 3-StateBus-DrivingOutputs FullParallelAccessforLoading BufferedControlInputs Clock-EnableInputHasHysteresisto ImproveNoiseRejection(’S373and’S374) P-N-PInputsReduceDCLoadingonData Lines(’S373and

SN74LS373

具有三態(tài)輸出的八路 D 類透明鎖存器; ? Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package\n? 3-State Bus-Driving Outputs\n? Full Parallel Access for Loading\n? Buffered Control Inputs\n? Clock-Enable Input Has Hysteresis to Improve Noise Rejection (?S373 and ?S374)\n? P-N-P Inputs Reduce DC Loading on Data Lines (?S373 and ?S374);

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.\n The eight latches of the ?LS373 and ?S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.\n The eight flip-flops of the ?LS374 and ?S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.\n Schmitt-trigger buffered inputs at the enable/clock lines of the ?S373 and ?S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.\n OC\\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.\n \n

SN74LS373

Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop WITH 3-STATE OUTPUT;

Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output\n\nThe SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.\nThe SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families.\n\n?Eight Latches in a Single Package\n?3-State Outputs for Bus Interfacing\n?Hysteresis on Latch Enable\n?Edge-Triggered D-Type Inputs\n?Buffered Positive Edge-Triggered Clock\n?Hysteresis on Clock Input to Improve Noise Margin\n?Input Clamp Diodes Limit High Speed Termination Effects

SN74LS373

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN74LS373

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN74LS373

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN74LS373

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SN74LS373DW

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT

OCTALTRANSPARENTLATCHWITH3-STATEOUTPUTS;OCTALD-TYPEFLIP-FLOPWITH3-STATEOUTPUT TheSN54/74LS373consistsofeightlatcheswith3-stateoutputsforbusorganizedsystemapplications.Theflip-flopsappeartransparenttothedata(datachangesasynchronously)whenLatchEnable(LE)

SN74LS373DW

Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output

OctalTransparentLatchwith3-StateOutputs;OctalD-TypeFlip-Flopwith3-StateOutput TheSN74LS373consistsofeightlatcheswith3-stateoutputsforbusorganizedsystemapplications.Theflip-flopsappeartransparenttothedata(datachangesasynchronously)whenLatchEnable(LE)is