SN74LS175DR屬于集成電路（IC）的觸發(fā)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74LS175DR觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類(lèi)型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

“174, 'LS174, ‘S174 Contain Six Flip-Flops

with Single-Rail Outputs

‘175, 'L.S175, ‘S175 Contain Four Flip-Flops

with Double-Rail Outputs

Three Performance Ranges Offered: See

Table Lower Right

Buffered Clock and Direct Clear Inputs

Individual Data Input to Each Flip-Flop

Applications include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

description

These monolithic, positive-edge-triggered flip-flops

utilize TTL circuitry to implement D-type flip-flop logic.

All have a direct clear input, and the ‘175, ‘LS175, and

$175 feature complementary outputs from each flip-

flop.

Information at the D inputs meeting the setup time

requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. Clock triggering

occurs at a particular voltage level and is not directly

related to the transition time of the positive-going pulse.

When the clock input is at either the high or low level,

the D input signal has no effect at the output.

These circuits are fully compatible for use with most

TTL circuits.