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SN74LS112A

具有清零和預置端的雙路負邊沿觸發(fā)式 J-K 觸發(fā)器; ? Fully Buffered to Offer Maximum Isolation from External Disturbance\n? Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n? Dependable Texas Instruments Quality and Reliability;

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C. ?

SN74LS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

SN74LS112A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

SN74LS112A

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

SN74LS112AD

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

SN74LS112AD

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

SN74LS112AD

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

SN74LS112ADE4

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

SN74LS112ADR

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

SN74LS112ADR

DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS