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SN74HC166

SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve

SN74HC166

8 位并行負(fù)載移位寄存器; ? Wide Operating Voltage Range of 2 V to 6 V\n? Outputs Can Drive Up To 10 LSTTL Loads\n? Low Power Consumption, 80-μA Max ICC\n? Typical tpd = 13 ns\n? ±4-mA Output Drive at 5 V\n? Low Input Current of 1 μA Max\n? Synchronous Load\n? Direct Overriding Clear\n? Parallel-to-Serial Conversion;

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR)\\ input. The parallel-in or serial-in modes are established by the shift/load (SH/LD)\\ input. When high, SH/LD\\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\\ overrides all other inputs, including CLK, and resets all flip-flops to zero.

SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SN74HC166

8-BIT PARALLEL-LOAD SHIFT REGISTERS

SN74HC166D

絲印：HC166；Package：SOIC；SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve

SN74HC166DB

SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve

SN74HC166DBR

絲?。?a target="_blank" title="Marking" href="/hc166/marking.html">HC166；Package：SSOP；SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve

SN74HC166DR

絲?。?a target="_blank" title="Marking" href="/hc166/marking.html">HC166；Package：SOIC；SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve

SN74HC166DRE4

絲?。?a target="_blank" title="Marking" href="/hc166/marking.html">HC166；Package：SOIC；SNx4HC166 8-Bit Parallel-Load Shift Registers

1Features ?Wideoperatingvoltagerangeof2Vto6V ?Outputscandriveupto10LSTTLloads ?Lowpowerconsumption,80-μAmaxICC ?Typicaltpd=13ns ?±4-mAoutputdriveat5V ?Lowinputcurrentof1μAmax ?Synchronousload ?Directoverridingclear ?Parallel-to-serialconve