SN74GTL16612DGGR屬于集成電路（IC）的通用總線功能。由美國(guó)德州儀器公司制造生產(chǎn)的SN74GTL16612DGGR通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過(guò)遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Members of Texas Instruments Widebus?

Family

· UBT? Transceivers Combine D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, Clocked, or

Clock-Enabled Modes

· OEC? Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

· Translate Between GTL/GTL+ Signal Levels

and LVTTL Logic Levels

· Support Mixed-Mode (3.3 V and 5 V) Signal

Operation on A-Port and Control Inputs

· Identical to '16601 Function

· Ioff Supports Partial-Power-Down Mode

Operation

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors on

A Port

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Latch-Up Performance Exceeds 500 mA Per

JESD 17

DESCRIPTION/ORDERING INFORMATION

The 'GTL16612 devices are 18-bit UBT? transceivers that provide LVTTL-to-GTL/GTL+ and

GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for

transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The

devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at

GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced

input threshold levels, and OEC? circuitry.

The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred

higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative

of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or

GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V

tolerant. VREF is the reference input voltage for the B port.

VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A

data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored

in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs

are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that

for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow through the device when it is powered down.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.