SN74AVC16334DGGR屬于集成電路（IC）的通用總線功能。由美國德州儀器公司制造生產(chǎn)的SN74AVC16334DGGR通用總線功能通用總線功能系列產(chǎn)品是元件級產(chǎn)品，用于處理或操作一系列（通常為 8 個或更多）并行邏輯信號（稱為總線）。所執(zhí)行的功能包括臨時存儲要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過遠距離互連高速傳輸數(shù)據(jù)，以及調換或移動總線內的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· DOC? (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,

Resulting in Noise Reduction Without Speed

Degradation

· Dynamic Drive Capability Is Equivalent to

Standard Outputs With IOH and IOL of ±24 mA

at 2.5-V VCC

· Overvoltage-Tolerant Inputs/Outputs Allow

Mixed-Voltage-Mode Data Communications

· Ioff Supports Partial-Power-Down Mode

Operation

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DESCRIPTION

A Dynamic Output Control (DOC?) circuit is implemented, which, during the transition, initially lowers the output

impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows

typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At

the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a

high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family

Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC?) Circuitry

Technology and Applications, literature number SCEA009.

This 16-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to

3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode

when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at

a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of

CLK. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.