SN74AVC16245DGGR屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74AVC16245DGGR緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· DOC? (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,

Resulting in Noise Reduction Without Speed

Degradation

· Less Than 2-ns Maximum Propagation Delay

at 2.5-V and 3.3-V VCC

· Dynamic Drive Capability Is Equivalent to

Standard Outputs With IOH and IOL of ±24 mA

at 2.5-V VCC

· Overvoltage-Tolerant Inputs/Outputs Allow

Mixed-Voltage-Mode Data Communications

· Ioff Supports Partial-Power-Down Mode

Operation

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

· Latch-Up Performance Exceeds 250 mA Per

JESD 78

· Package Options Include Plastic Thin Shrink

Small-Outline (DGG) and Thin Very

Small-Outline (DGV) Packages

DESCRIPTION

A Dynamic Output Control (DOC?) circuit is implemented, which, during the transition, initially lowers the output

impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows

typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At

the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a

high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family

Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC?) Circuitry

Technology and Applications, literature number SCEA009.