SN74AUP1G125DPW屬于集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN74AUP1G125DPW緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

1 Features

1? Available in the Texas Instruments NanoStar?

Package

? Low Static-Power Consumption

(ICC = 0.9 μA Maximum)

? Low Dynamic-Power Consumption

(Cpd = 4 pF Typical at 3.3 V)

? Low Input Capacitance (CI = 1.5 pF Typical)

? Low Noise – Overshoot and Undershoot

< 10% of VCC

? Input-Disable Feature Allows Floating Input

Conditions

? Ioff Supports Partial-Power-Down Mode Operation

? Input Hysteresis Allows Slow Input Transition and

Better Switching Noise Immunity at Input

? Wide Operating VCC Range of 0.8 V to 3.6 V

? 3.6-V I/O Tolerant to Support Mixed-Mode Signal

Operation

? tpd = 4.6 ns Maximum at 3.3 V

2 Applications

? Audio Dock: Portable

? BluRay? Players and Home Theaters

? Personal Digital Assistant (PDA)

? Power: Telecom/Server AC/DC Supply: Single

Controller: Analog and Digital

? Solid-State Drive (SSD): Client and Enterprise

? TV: LCD/Digital and High-Definition (HDTV)

? Tablet: Enterprise

? Wireless Headsets, Keyboards, and Mice

3 Description

The SN74AUP1G125 bus buffer gate is a single line

driver with a 3-state output. The output is disabled

when the output-enable (OE) input is high. This

device has the input-disable feature, which allows

floating input signals.

To ensure the high-impedance state during power up

or power down, OE must be tied to VCC through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.