SN74ALVCH373DW屬于集成電路（IC）的鎖存器。由美國德州儀器公司制造生產(chǎn)的SN74ALVCH373DW鎖存器鎖存器是類似于觸發(fā)器的基本數(shù)字存儲設(shè)備，但是不同之處在于，在鎖存使能（或類似命名）信號處于有效邏輯狀態(tài)的任何時間，保持的邏輯狀態(tài)都可以改變?！巴该鳌辨i存器還允許設(shè)備輸出在鎖存使能信號有效時反映輸入的當前狀態(tài)，而相反的是，狀態(tài)僅在保持狀態(tài)已固定時改變。

FEATURES

· Operates From 1.65 V to 3.6 V

· Max tpd of 3.3 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,

and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When

LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.