SN74ALVCH16821DLR屬于集成電路（IC）的觸發(fā)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALVCH16821DLR觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類(lèi)型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 20-bit bus-interface flip-flop is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH16821 can be used as two 10-bit

flip-flops or one 20-bit flip-flop. The 20 flip-flops are

edge-triggered D-type flip-flops. On the positive

transition of the clock (CLK) input, the device

provides true data at the Q outputs.

A buffered output-enable (OE) input can be used to

place the ten outputs in either a normal logic state

(high or low logic levels) or the high-impedance state.

In the high-impedance state, the outputs neither load

nor drive the bus lines significantly. The

high-impedance state and increased drive provide the

capability to drive bus lines without need for interface

or pullup components.

OE does not affect the internal operation of the

flip-flops. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.