SN74ALVCH16524DLR屬于集成電路（IC）的通用總線功能。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALVCH16524DLR通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱(chēng)為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過(guò)遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· UBT? Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, Clocked, or

Clock-Enable Mode

· Operates From 1.65 V to 3.6 V

· Max tpd of 3.2 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA) and clock-enable

(CLKENBA) inputs. For the A-to-B data flow, the data

flows through a single buffer. The B-to-A data can

flow through a four-stage pipeline register path, or

through a single register path, depending on the state

of the select (SEL) input.

Data is stored in the internal registers on the

low-to-high transition of the clock (CLK) input,

provided that the appropriate CLKENBA input is low.

The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.