最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

SN74ALVCH162721

具有三態(tài)輸出的 3.3V 20 位觸發(fā)器; ? Member of the Texas Instruments Widebus? Family\n? EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process\n? Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required\n? ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)\n? Latch-Up Performance Exceeds 250 mA Per JESD 17\n? Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors\n? Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages\nNOTE: For tape and reel order entry: The DGGR package is abbreviated to GR. Widebus, EPIC are trademarks of Texas Instruments.;

This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCC operation.\n The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\\ input is low. If CLKEN\\ is high, no data is stored.\n A buffered output-enable (OE)\\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.\n To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.\n Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.\n The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.\n The SN74ALVCH162721 is characterized for operation from ?40°C to 85°C.\n \n

SN74ALVCH162721

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721_08

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DGG

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DGG

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DGGR

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DL

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DL

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH162721DLR

3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS