SN74ALVCH16270DLR屬于集成電路（IC）的通用總線功能。由美國德州儀器公司制造生產(chǎn)的SN74ALVCH16270DLR通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16270 is used in applications in

which data must be transferred from a narrow

high-speed bus to a wide lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate CLKEN inputs are

low. The select (SEL) line selects 1B or 2B data for

the A outputs. For data transfer in the A-to-B

direction, a two-stage pipeline is provided in the

A-to-1B path, with a single storage register in the

A-to-2B path. Proper control of the CLKENA inputs

allows two sequential 12-bit words to be presented

synchronously as a 24-bit word on the B port. Data

flow is controlled by the active-low output enables

(OEA, OEB). The control terminals are registered to

synchronize the bus-direction changes with CLK.

To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as

possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the

outputs cannot be determined prior to the arrival of the first clock pulse.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16270 is characterized for operation from -40°C to 85°C.