SN74ALVCH162268DLR屬于集成電路（IC）的通用總線功能。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALVCH162268DLR通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過(guò)遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· Operates From 1.65 V to 3.6 V

· Max tpd of 4.8 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· B-Port Outputs Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162268 is used for applications in

which data must be transferred from a narrow

high-speed bus to a wide, lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate clock-enable

(CLKEN) inputs are low. The select (SEL) line is

synchronous with CLK and selects 1B or 2B input

data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single

storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be

presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables

(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot

and undershoot.