SN74ALS869DWE4屬于集成電路（IC）的計(jì)數(shù)器除法器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALS869DWE4計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡(jiǎn)單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

Fully Programmable With Synchronous

Counting and Loading

SN74ALS867A and 4AS867 Have

Asynchronous Clear; SN74ALS869 and

4AS869 Have Synchronous Clear

Fully Independent Clock Circuit

Simplifies Use

Ripple-Carry Output for n-Bit Cascading

Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

description

These synchronous, presettable, 8-bit up/down

counters feature internal-carry look-ahead

circuitry for cascading in high-speed counting

applications. Synchronous operation is provided

by having all flip-flops clocked simultaneously so

that the outputs change coincidentally with each

other when so instructed by the count-enable

(ENP, ENT) inputs and internal gating. This mode

of operation eliminates the output counting spikes

normally associated with asynchronous (rippleclock)

counters. A buffered clock (CLK) input

triggers the eight flip-flops on the rising (positivegoing)

edge of the clock waveform.

These counters are fully programmable; they may

be preset to any number between 0 and 255. The

load-input circuitry allows parallel loading of the

cascaded counters. Because loading is

synchronous, selecting the load mode disables

the counter and causes the outputs to agree with

the data inputs after the next clock pulse.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental

in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined

by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO

thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting

up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages.

Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize

transmission-line effects, thereby simplifying system design.

These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the

SN74ALS867A and 4AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q

outputs until clocking occurs. For the 4AS867 and 4AS869, any time ENP and/or ENT is taken high, RCO either

goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes

or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely

by the conditions meeting the stable setup and hold times.