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SN74ALS561AN.A中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

廠商型號(hào) |
SN74ALS561AN.A |
功能描述 | SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS |
絲印標(biāo)識(shí) | |
封裝外殼 | PDIP |
文件大小 |
315.95 Kbytes |
頁面數(shù)量 |
12 頁 |
生產(chǎn)廠商 | TI2 |
中文名稱 | 德州儀器 |
網(wǎng)址 | |
數(shù)據(jù)手冊 | |
更新時(shí)間 | 2025-8-7 8:31:00 |
人工找貨 | SN74ALS561AN.A價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
SN74ALS561AN.A規(guī)格書詳情
Carry Output for n-Bit Cascading
Buffer-Type Outputs Drive Bus Lines
Directly
Choice of Asynchronous or Synchronous
Clearing and Loading
Internal Look-Ahead Circuitry for Fast
Cascading
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These binary counters are programmable and
offer synchronous and asynchronous clearing as
well as synchronous and asynchronous loading.
All synchronous functions are executed on the
positive-going edge of the clock.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). ACLR (direct clear)
overrides all other functions of the device, while
SCLR overrides only the other synchronous
functions. Data is loaded from the A, B, C, and D
inputs by applying a low level to asynchronous
load (ALOAD) or by the combination of a low level
at synchronous load (SLOAD) and a
positive-going clock transition. The counting
function is enabled only when enable P (ENP),
enable T (ENT), ACLR, ALOAD, SCLR, and
SLOAD are all high.
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces
a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is
enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated
with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter
to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because
CCO does not become active until the clock returns to the low level.
The SN54ALS561A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS561A is characterized for operation from 0°C to 70°C.
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---|---|---|---|---|---|---|---|
TI |
2025+ |
SOIC-20 |
16000 |
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詢價(jià) | ||
Texas Instruments |
2022+ |
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8600 |
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TI(德州儀器) |
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7350 |
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TI(德州儀器) |
24+ |
PDIP20 |
1476 |
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TI(德州儀器) |
2024+ |
- |
500000 |
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Texas Instruments |
25+ |
20-DIP(0.300 7.62mm) |
9350 |
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TI |
22+ |
20PDIP |
9000 |
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詢價(jià) | ||
24+ |
3000 |
自己現(xiàn)貨 |
詢價(jià) | ||||
TI |
24+ |
SOP |
6868 |
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詢價(jià) | ||
Texas Instruments(德州儀器) |
22+ |
NA |
500000 |
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